In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products.
Remote is an option too.
Key Qualifications :
Experience in custom RF / analog layout with extensive knowledge of deep sub-micron CMOS (40nm, 28nm, FinFet, etc.)
Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing
Must have experience in 7nm or less
Solid understanding of RC delay, electro migration, and coupling
Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
Knowledge of CADENCE layout toolsAs an RF Engineer, you will be responsible for :
Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC / DAC, baseband filters, and bandgap / bias / LDO.
Block level and top-level layout through full verification flow including extraction, DRC, LVS, and DFM checking
Co-work with designers on block level and top-level floorplanning
Layout review for power / gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling
Skills & Experience
Cadence Virtuoso, Custom Layout Design, Radio-Frequency Integrated Circuit (RFIC)
Cyient is an Equal Opportunity Employer.